Scott J Weber

Viterbi IP

For a demonstration of Viterbi check out this Viterbi Applet.

The information below comes from a combination of company web sites, product datasheets,
and email correspondence with company representatives. The information I got back from the
representatives was informative on mostly pricing and licensing. Not all of the companies
responded to my requests, but the ones that did have their responses summarized along with
the other data I found for each IP block.

Inventra

Description:   Inventra Viterbi Encoder/Decoder datasheet

Inventra provides the ability to parameterize solutions as the datasheet explains. Below are
some possible configurations that could be purchased from Inventra. Each generated configuration
is a HDL soft core.

Resource-Shared Parameterized Implementations (Area-Efficient Implementations)

A specific resource-shared implementation is shown and characterized below. The definitions
of the parameters can be found in the datasheet. The following specific characteristics were extracted
for the configuration. Values on performance are post-synthesis done in-house at Mentor Graphics. The
values assume a 0.35um CMOS process under nominal conditions.
 

Performance

For the configuration shown above, the clock rate was found to be 96.584 MHz post-synthesis. The
sample rate was found to be 96.584 MHz post-synthesis.

Power

Power numbers were not reported. Power numbers are dependent on the synthesis.

Cost

The above configuration was found to be 12034 gates post-synthesis. Specific licensing conditions
were not discussed in the web page, but a price of $92,160.00 was listed for a purchase price of the
IP. Conditions on the purchase were not found.

Use Model

The IP block is soft and would be delivered as RTL HDL. Specifics on what else is delivered with the
IP was not found (i.e. synthesis scripts, test vectors, test benches).

Non-Resource-Shared Parameterized Implementations (High Speed Implementations)

A specific non-resource-shared implementation is shown and characterized below. The definitions
of the parameters can be found in the datasheet. The following specific characteristics were extracted
for the configuration. Values on performance are post-synthesis done in-house at Mentor Graphics. The
values assume a 0.35um CMOS process under nominal conditions.
 

Performance

For the configuration above, the clock rate was found to be 103.133 MHz. The sample rate was not found,
but since this is a non-resource-shared implementation it should be faster than the resource-shared
implementation.

Power

Power numbers were not reported. Power numbers are dependent on the synthesis.

Cost

The above configuration was found to be 107341 gates post-synthesis. Specific licensing conditions
were not discussed in the web page, but a price of $92,160.00 was listed for a purchase price of the
IP. Conditions on the purchase were not found.

Use Model

The IP block is soft and would be delivered as RTL HDL. Specifics on what else is delivered with the
IP was not found (i.e. synthesis scripts, test vectors, test benches).

Other implementation estimates can be found on the datasheet.

The Inventra parameterizable viterbi decoder web page was easy to use. I could get results
on performance for any set of parameters that I specified. It was useful to examine the
different configurations. The cost for the core was rather high and this core would only make
sense in high volume applications.

For further information, one should contact Inventra directly.

Alantro

Description:  Alantro 64-State Viterbi Encoder/Decoder datasheet

For a general description and features of this viterbi soft core check out the datasheet.

Performance

The estimated sample rate from Alantro was 25Mbs.

Power

Specific power numbers were not listed, but the data sheet states that the IP block was
optimized for power/area. Power could be determined after synthesis.

Cost

A standard design requires approximately 26,000 gates in addition to 16k bits of single
port RAM.

Use Model

It is a soft core that comes as synthesizable Verilog-HDLwith Synopsys synthesis scripts,
test-vector files, and Verilog test benches included. The cost for the core is $40,000.00 with
a royalty structure based on volume.

The Alantro core datasheet was limited in details. A company representation gave
me most of the information on cost and licensing and performance. The cost is rather
high. It should not be to difficult to integrate the core since it comes with synthesis scripts,
and test benches.

For further information, one should contact Alantro directly.

Signal Processing Associates

Description:  Signal Processing Associates Viterbi datasheet

For a general description and features of this Viterbi software designed for the Analog
Devices ADSP-21xx series of DSP chips check out the datasheet. The application can be
configured for various flavors of Viterbi.

Performance

Performance estimates were not shown and are dependent on the configuration.

Power

Power estimates were not shown.

Cost

Price figures and information on licensing were not immediately available. Code and data
size requirements are listed below:
 

Use Model

The model is delivered as library files and demonstration files for use with the ADSP-21xx
series DSP chip from Analog Devices. It is software that can be loaded onto the DSP.

This solution would be easy to implement. It would require loading the code on the DSP. The
software solution is very low in comparison to the previous cores. I cannot state the actual
parameters because the information is confidential, but I know it is high. The cost is also quite
high and would only be sensible in high volume applications. The information on the core
was given to me in confidence very quickly, but like most of the companies are low on the
information that they provide for their products, and if they do give you information they want
it to be confidential.

For further information, one should contact Signal Processing Associates directly.

Hantro

Description:  Hantro Soft Decision Viterbi datasheet

For a general description and features of this Soft Decision Viterbi Decoder check
out the datasheet. A number of parameters for this soft IP can be configured for the
customer. These configurations are again shown in the datasheet. A specific configuration
for the Altera EPF10K10 is shown below to demonstrate certain aspects of the core.

The parameters shown below can be customized. In our specific example here, these
were the numbers used.
 

The results of this implementation on the EPF10K10 results in the following:

Performance

This implementation on the FPGA results in an operating frequency of 45 MHz.

Power

Power numbers were not shown in the documentation. Altera has some information
on power specifics for their Altera EPF10K10.

Cost

The cost for the core is not given. Licensing issues are not discussed either. An EPF10K10
would have to be purchased in order to implement this particular solution. The following
LC and RAM cost figures on the FPGA are given. This is only of concern if more functionality
is to be implemented on the same FPGA.
 

Use Model

The following items are delivered with the VHDL source licenses sold for the IP:
  VHDL RTL source code Testbench Example testbench wrapper for post-route simulation Vectors for testbench Simulation script Synthesis script Expected results for testbench

This is a sensible implementation for the Altera. Good information on the product was given,
but again not all the information could be found. Implementing the solution would require synthesizing
the RTL and then downloading the resulting configuration to the FPGA.

For further information, one should contact Hantro directly.

CAST

Description:  CAST Soft Decision Viterbi datasheet

For a general description of this Soft Decision Viterbi Decoder check out the datasheet. A
number of parameters for this soft IP can be configured for the customer. These configurations
are again shown in the datasheet.

The parameters shown below can be customized. In our specific example here, these
were the numbers used. These parameters and this specific parameterization can be found
in the datasheet. The example target architecture was the Xilinx Virtex.
 

Performance

The data rate can be found in general from the following equation:

Data rate =  (Clock Frequency / (2^(K-1) / (Number of ACS elements)))

K = 7
Clock Frequency = 60 MHz
Number of ACS elements = 4

Data rate = (60 MHz / (2^(7-1) / 4)) = 3.75 MHz.

Power

No power numbers were shown for the implementations. General information on power can
be found for the Xilinx Virtex.

Cost

Both of the implementations require the use of 425/576 CLBs and 109/191 IOBs.

Use Model

The core can be delivered as a VHDL source RTL file or as a firm XNF netlist.
A netlist format is $17,500.00 and a RTL verison is $32,000.00. These prices are for a one
time site license. Annual support and maintenance is available for at 15% of the sales price.
The product is delivered with test vectors, test benches, and expected results.

This was by far the most helpful company that I spoke with. They gave me the information
that I needed. The cost is high. Again implementing the solution would be as easy as
downloading the netlist or synthesizing the RTL and then downloading the resulting
netlist.

For further information, one should contact CAST directly.

Overall, it is hard to get anything of value out of these companies. They will never
tell you everything until you open communication with them. Emailing the companies
helped.