Szu-Tsung 
Cheng
Szu-Tsung Cheng graduated with a PhD from
Computer Science Division,
Department of EECS,
University of California at Berkeley
in May 1998.
His PhD research was on compilation, synthesis, and simulation of
Hardware Description Languages under the advisement of
Professor
Robert K. Brayton .
Where to find Szu-Tsung Cheng
Somewhere in UC Village
Albany, CA
xyz-xwu-ttsr
Office
Cadence Berkeley Laboratories
2001 Addison Street, Floor 3
Berkeley, California 94704
510-647-2831
Home-home
Taipei, Taiwan, R.O.C.
Projects
V++
Verilog to BLIFMV/SMV+ compiler
Verilog Source Debugger for
HSIS
KISS to BLIFMV translator
Superscalar DLX simulator
Design, Layout, and Simulatioin of a FPGA chip (Phoenix)
General purpose neural network simulator
C Information Abstractor - a project manager
ADA/CS compiler
Command, Control, Communication and Intelligence (C3I) system for military
Publications
Resume (gzipped postscript)
Expertise
Links
Friends
e-mail to Szu-Tsung Cheng.
CAD Group Homepage
Last Updated 6/25/98
Interesting sites
Linux
KTV