| Component | Description | Power | Cost | Area | Use Model | Comments
|
|---|
| Xilinx and CoreEL FPGA Ethernet media access controller | 10/100 Mbit/s
| Estimate 200W on XC4005s if all CLBs in use. | $12,500 | 71K gates, 932 CLBs. | VHDL, programmable logic on XC4000 FPGA | 25 MHz clock.
|
| Inventra 10100ETH | 10/100 Mbit/s Ethernet controller. | technology dependent | | 60K gates | 32 bit PCI interface, 2.5 MHz or 25MHz clock | A lot of on chip support (buffering et al.).
|
| Inventra MAC | 10/100 Mbit/s Ethernet MAC. | technology dependent | | 17K gates | | Insufficient detail.
|
| Inventra GEM-PAK-STD | Gigabit Ethernet with MAC and flow control | technology dependent | | 10K gates | VHDL source | Synthesized for 0.5um, 125MHz clock.
|
| CoreEl Gigabit Ethernet MAC core | Gigabit Ethernet MAC. | technology dependent | | 14.5K gates | VHDL source | Synthesized for 0.35um and 0.5um CMOS, maximum clock frequency of 133MHz.
|
| LSI Logic E-110 | 10/100 Mbit/s | technology dependent | | | Verilog and VHDL models, operates at 2.5 MHz or 25 MHz | 98% fault coverage. No details on size, power or cost.
|
| YAGO Systems MSR Family | Multilayer switching router with 10/100 ports | technology dependent | $595/port | | Operates at 125MHz. Custom chipset ASIC with MIPS RISC VR5000 microprocessor. | Scalable architecture Ethernet router. 0.35um process. Also available with gigabit ports.
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| LANCore LC-GMC1000 | Gigabit Ethernet MAC. | technology dependent | one time fee | 15-25K gates RTL, 40K gates on ORCA 3C FPGA. | 66MHz interface. Verilog or VHDL RTL code and test benches. | Optimised for 0.35um CMOS, 3.3V or 5V operation, and ORCA 3C FPGA.
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