Table of Contents
Design Reuse: Can It Halt the SoC Train Wreck
The Irresistible Force
The Unmovable Object
Outline
Problems of Scale
Plate Tectonics— Shifts in IC Landscape
HW Productivity - Gates
HW Productivity - LOC
HW and SW Productivity
HW and SW Productivity
HW and SW Code Size
The Inflection Point
PPT Slide
How Will the Semiconductor Companies Achieve This Level of Reuse?
Consensus on the Model
Reuse Experience to Date
What’s Going Wrong
Management View
The CAD View
Engineering View
What Do We Do About It
Step 1: The value of Good Design
Case Study
Case Study - Importance of Locality
Short list of key design rules
Short list of key design rules
Step 2: Extend to reuse
Step 3: Lower the Cost
Step 4: The Rest of the Path
Managing the Culture Change
Synopsys’ Role
Summary— Journey of a Thousand Miles
PPT Slide
Supplemental Material
Taxonomy of IP
Third Party IP Landscape
Third Party IP Landscape
What’s Happening with 3rd Party IP
Why the Problems
Technical Issues
what sort of interface specification is good for components
how good are the estimates for IPs in terms of power, performance, area
Design for Reuse The Standard Model
Outline
Fundamental Goal
SoC Canonical Design
SoC - Sources of Blocks
Fundamental Approach
Corollary
Deliverables for IP
Soft vs Hard IP
Soft vs Hard IP
IP Deliverables
Deliverables
Design Guidelines for IP
Architecture and Interfaces
SoC Requires Scalability
Designs that don’t Scale
Internals -
Low Power Design for Reuse
Low Power Design for Reuse
Bus Interface Standards
Manufacturing Test
Manufacturing Test Strategy
Libraries and Memory
Prerequisites for Reuse
Prerequisites for Reuse
Foundry/Library Group
Functional Verification
Functional Test - IP
Functional Test - Chip
Summary
Summary
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