System-on-a-Chip IP Creation andAnalysis Flow

Chip Assembly

Block P&R

Memory Behavior

Model

Memory

Analog

Functional

Description

RTL

Logic

Synthesis

Logic Design

& Simulation

Logic

Verification

Core Cell

Sense Amp

Analog Functional

Model

Decoder/

Periphery Design

Analog Circuit

Design & Sim.

Final Power &

Reliability Check

Architectural Design

Performance

Optimization

Datapath

Compiler

Std Cell

P&R

Custom

Layout

Full Chip

Timing Verification

Full Chip

Func Simulation

DRC/LVS/Extraction

Parasitic Reduction

Digital Control

Datapath

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