The EDA Industry may be solving the wrong problem by focusing on deep-submicron interconnect delays, according to a controversial paper presented here at last week’s International Conference on Computer-Aided Design (IC-CAD’98). The paper shows new data claiming that interconnect delays will actually decrease at the 50,000 gate module level as feature sizes shrink. Source: EE Times 16Nov98

DQ Take: The amount of confusion within the CAD community has been the big surprise in the effort to develop System Level Integration (SLI) design methodology. Most of the engineers are getting overwhelmed by the magnitude of the problem. Fortunately there is a small group that see this as a very familiar challenge. For those that were around, in the first days of the Gate Array industry, these problems just aren’t that unique. It’s a testimony, to those early methodologist, that they solved the problems so well, that most of today’s engineers don’t even recognize them as problems. This is like PC Board design ! The difference being that PCBs of the late 1970s were populated mainly with SSI (Small Signal Integration) ICs. Where do you think the gate came from. And from the gate came the 200 to 400 basic elements of today’s ASIC library. Hasn’t changed in twenty years. Richard Goering’s article is a great collection of comments from the people who don’t get it. How do you design a million gate IC ? Well, with a million gates. Fortunately Kurt Keutzer gets it. The first thing we needed to know was the optimum size of a basic SLI library element. The work, at Berkeley, now tells us it’s 50,000 gates. So we have defined today’s SSI. Now the challenge is to develop the 200 to 400 basic library elements needed to really do SLI design. Does sound familiar doesn’t it ?

Gary Smith at (408)468-8271 Smith@dataquest.com