Defying convention, pair states interconnect delays are decreasing

By Richard Goering
EE Times
(11/11/98, 5:33 p.m. EDT)

SANTA CLARA, Calif. — The EDA industry may be barking up the wrong tree by trying to merge synthesis with layout, according to a controversial paper delivered Monday (Nov. 9) at the International Conference on Computer-Aided Design (ICCAD '98). The paper presented new data stating that interconnect delays will actually decrease at the 50,000-gate module level as feature sizes shrink.

Presented by Kurt Keutzer, professor of electrical engineering and computer science at the University of California at Berkeley, and Dennis Sylvester, a graduate student, the paper flies in the face of current “industry wisdom,” which holds that interconnect delays will dominate deep-submicron design. Industry vendors contend that logical and physical design must merge to solve that problem.

The intent of the paper was to apply analytical models and empirical design data to gauge the precise impact of interconnect delays. The paper concludes: with proper drive strengths, delays at the 50,000-gate module level are not driven by interconnect; delay degradation from power can be eliminated; and power dissipation remains “nearly constant” as feature sizes move from 0.25 microns to 0.1 microns.

But these conclusions start to fall apart as modules get much larger than 50,000 gates, suggesting that the best approach to a 10-million-gate chip may be to partition it into two-hundred 50,000-gate blocks. That could be a tremendous design challenge, as could the global routing necessary to connect all those blocks.

Keutzer, who until recently was chief technology officer at Synopsys Inc. (Mountain View, Calif.), said that a year ago he too was spreading the gospel about the impact of interconnect delays. But all that suddenly changed. “I became de-converted about the notion of uniting synthesis with physical design,” he said. “You can do 50,000- to 100,000-gate modules without a new methodology, as long as you have sufficient drive strengths.

“The real problem is global interconnect, and that's a problem of global routing,” said Keutzer. “That's not a problem of synthesis and layout.”

Synopsys, Keutzer's former employer, seems to be listening to his ideas. At the IEEE International ASIC Conference in September, Raul Camposano, Synopsys' current CTO, offered a controversial preview of Keutzer's then-unpublished paper. Further, Synopsys just purchased Everest Design Automation, which Keutzer said is doing “the most intelligent job I've seen” with global routing.

Keutzer acknowledged that partitioning a huge chip into 50,000-gate blocks is not a trivial task. “But what are the choices?” he asked. “I think we've done our homework. We invite anyone else to come forward with an alternative methodology.”

In presenting the paper at ICCAD, Keutzer and Sylvester outlined an approach that combined ASIC design data from Symbios Inc. with analytical models and process data, including interconnect and device parameters. The authors started with 0.35-micron design data and used a “shrink” process to take it down to 0.05 microns.

One point made by the paper is that “interconnect delay” is a poorly defined term. The paper proposes that interconnect delay is the difference between stage delay and intrinsic gate delay, as modeled by 2-input NAND ring oscillators and average wire lengths.

Due to shrinking gate pitches, the paper concludes, local wirelengths will shrink with process scaling. In fact, the authors forecast a decrease in average wiring capacitance by a factor of 12 from 0.25 microns to 0.05 microns due to shorter lines and low-K dielectrics.

What this means, Sylvester said, is that interconnect delays will be around 30 to 40 percent of total delay at 0.25 microns, and in the 23 to 30 percent range at 0.1 microns — a far cry from the 80 percent figure currently bandied about by EDA and semiconductor vendors.

But once again, these figures change dramatically as module size grows. Sylvester said that a 100,000-gate module will have 28 percent longer wires, and interconnect delays of 10 to 13 percent over an optimal 50,000-gate module. A 200,000-gate module will have 79 percent longer wires and an interconnect delay increase of 26 to 32 percent.

The paper acknowledges that noise will result in increased stage delays, due to higher effective capacitance and larger power dissipation. But even considering noise effects, it predicts a drop in the ratio of interconnect delay to total delay, from 55 percent at 0.25 microns to 39 percent at 0.1 microns.

To gauge the impact of CMOS scaling on dynamic power consumption, the paper described a model that includes such factors as packing density, wiring pitches, average device size, and routing density. The conclusion is that power density at the 50,000-gate module level is not increasing significantly despite the rise in clock frequency.

The paper contrasted sharply with the conclusions in the SIA's National Technology Roadmap for Semiconductors. Sylvester said the road map doesn't reflect optimal gate sizing, or consider that at the local level, wire lengths get shorter as logic becomes more dense.

There is an important assumption behind all of these conclusions — the results presume that lines are adequately driven to compensate for capacitive loads and noise effects. Design flows must ensure accurate timing and noise analysis, and sufficient cell sizing. Keutzer said EDA tools must provide better ways of adjusting drive strength.

John Darringer, manager for EDA strategy at IBM's Server Group, was in the audience, and later noted that the paper reflects the kind of advanced modeling work that needs to be done. But “it doesn't tell me how to design a 40-million gate chip,” he said.

A short feedback session at ICCAD revealed a some skepticism about the paper and about various assumptions and metrics it used. Keutzer responded by inviting participants to plug their own data into the system-level performance model developed for this research, which is part of the new Berkeley Advanced Chip Performance Calculator (BACPAC). The model is available online.

Keutzer and Sylvester's presentation slides are also available online.

All material on this site Copyright © 1998 CMP Media Inc. All rights reserved.

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