Introduction to Computer Aided Design of Integrated Circuits - Fall 2005

Prof. Kurt Keutzer (keutzer@eecs.berkeley.edu)

Prof. Sanjit A. Seshia (sseshia AT eecs.berkeley.edu)   (Office hours: Thu 2:30 - 3:30 pm)

Monday / Wednesday 2:30 - 4:00 PM
540A Cory Hall

EECS244 CCN: 25748
Units of Credit: 3

Introduction

Integrated circuits are so complex that they require a sophisticated battery of algorithms and software design tools to aid in their design. Because the complexity and performance of integrated circuits is evolving exponentially the techniques and tools used to aid in their design are constantly evolving as well. This course reviews the most fundamental algorithms and techniques underlying today's integrated circuit design approaches, and also gives some context for new problems.

This course may be of interest to a number of types of students. The first are graduate students in the area of computer-aided design. For these students it provides a one-semester introduction to the area and a review of a significant amount of the material for preliminary examinations in computer-aided design. A second type are those students principally interested in the design of digital integrated-circuits. For students embarking on a lifetime of using computer-aided design tools to design circuits, some time spent in understanding the principles underlying these tools will be well invested. A third class of students are those interested in exploring the frontier between technology CAD areas such as device and process modeling and mainstream CAD. With the increasing impact of processing effects on integrated circuits in small process geometries this has been an especially fruitful area of CAD research. Finally, this course may also be of interest to computer science students who are interested in seeing a wide variety of practical applications of algorithms and mathematical programming techniques such as: shortest/longest path; all-pairs shortest path; union-find; dynamic programming; string-matching; linear-programming; non-linear programming; branch and bound; and backtracking.

Course Structure

Course material will be presented in a series of lectures over the semester. The syllabus is below. Course grade will depend on:

  • Exam 1: 30%
  • Exam 2: 30%
  • Class project: 40%

The class project may be either a theoretical or practical investigation of open problems in areas discussed in the course.

Course Materials

  • Course Reader
  • Logic Synthesis   S. Devadas, A. Ghosh, K. Keutzer, McGraw Hill (recommended, get from Amazon)

 

Course Project Ideas

  • Class project ideas
  • Another project idea
  • More project ideas (UPDATED)

Course Prerequisites

The catalog lists EE140 or EE141 as a prerequisite, but that is not really necessary. It would be useful to have some basic understanding of circuits and digital logic at the CS150 level. It would also be useful to have some background in algorithms at the CS170 level, but this is not essential. It is expected that students have some background in one of circuits, algorithms, or software engineering. If you don't have a strength in any one of these the course will be tough.

Course Schedule

Date

Lecture/Topic

Milestones

Lecture Notes

Readings

8/29

1- Introduction to CAD -KK

 

 1-1-cad-overview.pdf

 

8/31

2- Introduction to RTL Design -KK

 

  1-2-rtl-overview.pdf

 

9/7

3,4 - Timing Analysis and Timing Optimization - KK

Project Teams

Brief proposal

timing_pdf

Logic Synthesis, DGK, 8.1 - 8.2

9/12

 

9/14

9/19

5 Partitioning,  - KK

 

 3-1-partition.pdf

Reader: Kernighan and Lin (1)
Fiduccia and Mattheyses (2)

6 Placement - KK

3-2-placement.pdf

GORDIAN (3)

9/21

7 Routing - KK

 

4-routing.pdf

Reader: Kuh (4), Rivest and Fiduccia (5)
Yoshimura and Kuh (6)
C. Y. Lee (7)

9/26

8 Compaction -SS

 

 5-compaction.pdf

 

9/28

9 Two-level logic optimization - SS

 

 6-two-level.pdf

Devadas and Keutzer - Chapter 3 & 4

10/3

10 Multilevel Logic Optimization - SS

6-2-multilevel.pdf

Devadas and Keutzer - Sections 6.1, 6.2, 7.1 - 7.6

10/5

11 Technology Mapping - KK

 Exam 1 handed out & Full Proposal due

7-1-techmap.pdf

 

Devadas and Keutzer, Ch. 7.7-7.9, 8.4-8.6

10/10

12 Retiming - SS

 

 8-2-retiming

N. Shenoy

10/12

13 Algorithm review - KK

Exam 1 due 

 8-1-alg-rev

 

10/17

14 Project discussion/Midterm review - SS/KK

 

 9-1-midterm-review

 9-project-review

 

10/19

15 Stuck-at Testing - SS

 

 9-1-testing

Logic Synthesis, Ch. 9
T. Larrabee

10/24

16 Delay Test - KK

 

 10-1-testing-enhanced

Logic Synthesis Ch5, Ch9

10/26

17 Implementation Verification- SS

 

  10-1-verification

Logic Synthesis, Ch. 6.3-6.4

10/31

18 The Register-Transfer Level - KK

 

11-1-rtl-review-and-problems

Logic Synthesis, Ch. 2

11/2

19 BDDs, Boolean Function Manipulation SS

 Preliminary Project Report due

  12-1-BooleanFunctions

 

11/7

20 Equivalence Checking of Sequential Circuits - SS

 

 12-2-SeqCktEC

 

11/9

21 Design Verification, Symbolic Evaluation - SS

  Exam 2 handed out

 10-2-design

 

11/14

22 Property specification and Model Checking - SS

 

 13-1-TemporalLogic

 

 

11/16

23 Model Checking - SS

  Exam 2 due

 13-2-ModelChecking

 

11/21

24 Guest lecture by Prof. A. Kuehlmann: DRC and LVS

 

 14-1-DRC_LVS

 

11/23

25 - What's the Next thing in EDA? - KK

 

 

 

11/28

26 - ASIP Architectures -KK

 

 

 

11/30

27 - ASIP Programming Models - KK

 

 

 

 

 

 

12/5

28, 29 Project Presentations

 Project presentation

 

 

12/7

 Project presentation

 

 


Last updated October 2, 2005
Copyright © 2005Kurt Keutzer