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Robert K. Brayton, Alberto Sangiovanni-Vincentelli, Adnan Aziz, Szu-Tsung Cheng, Stephen Edwards, Sunil Khatri, Yuji Kukimoto, Shaz Qadeer, Rajeev K. Ranjan, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa, Gary D. Hachtel, Fabio Somenzi, Abelardo Pardo, and Shaker Sarwary. VIS: A System for Verification and Synthesis. In Proc. of the 8th International Conference on Computer Aided Verificatio n, volume 1102 of Lecture Notes in Computer Science, pages 428-432. Springer-Verlag, 1996.

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Robert K. Brayton, Alberto Sangiovanni-Vincentelli, Adnan Aziz, Szu-Tsung Cheng, Stephen Edwards, Sunil Khatri, Yuji Kukimoto, Shaz Qadeer, Rajeev K. Ranjan, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa, Gary D. Hachtel, Fabio Somenzi, Abelardo Pardo, and Shaker Sarwary. VIS: Tutorial. In International Conference on Formal Methods in Computer-Aided Design (FMCAD), volume 1166 of Lecture Notes in Computer Science, pages 248-256. Springer-Verlag, 1996.

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Szu-Tsung Cheng and Robert K. Brayton. Synthesizing Multi-Phase HDL Programs. In Proceedings of International Verilog Conference. IEEE, March 1996.

5

M. Fujita, Y. Kukimoto, and R. K. Brayton. BDD Minimization by Truth Table Permutations. In Proceedings of International Conference on Circuits and Systems, volume IV, pages 596-599, May 1996.

6

E. Goldberg and R. Brayton. A New Method for Escaping Local Minima in Two-Level Minimization. In International Workshop on Logic Synthesis (submitted), 1997.

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E. Goldberg, Y. Kukimoto, and R. K. Brayton. Canonical TBDD's: A New Data Structure for Boolean Functions. In International Workshop on Logic Synthesis (submitted), May 1997.

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Evguenii I. Goldberg, Luca Carloni, Tiziano Villa, Robert K. Brayton, and Alberto L. Sangiovanni-Vincentelli. A Method for Incrementally Raising Lower Bounds Applied to Unate Covering. In International Workshop on Logic Synthesis (submitted), 1997.

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Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, and Alberto L. Sangiovanni-Vincentelli. Theory and Algorithms for Face Hypercube Embedding. In International Workshop on Logic Synthesis (submitted), 1997.

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R. Hojati, S. C. Krishnan, and R. K. Brayton. Early Quantification and Partitioned Transition Relations. In International Conference on Computer Design 1996, pages 12-19, October 1996.

11

Ramin Hojati, David L. Dill, and Robert K. Brayton. Verifying Linear Temporal Properties of Data Insensitive Controllers Using Finite Instantiations. In Conference on Hardware Decsription Lanaguages (CHDL) (to appear), 1997.

12

Ramin Hojati, Adrian Isles, and Robert K. Brayton. Optimizing Symbolic Execution of ICS Models Using State Reduction. In CAV97 (submitted), 1997.

13

Ramin Hojati, Adrian Isles, Desmond Kirkpatrick, and Robert K. Brayton. Verification Using Uninterpreted Functions and Finite Instantiations. In International Conference on Formal Methods in Computer-Aided Design (FMCAD), 1996.

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Ramin Hojati, Andreas Kuehlmann, Steven German, and Robert K. Brayton. Validity Checking in the Theory of Equality with Uninterpreted Functions Using Finite Instantiations. In International Workshop on Logic Synthesis (submitted), 1997.

15

Jain, Narayan, Coelho, Khatri, Sangiovanni-Vincentelli, Brayton, and Fujita. Decomposition Techniques for Efficient ROBDD Construction. In International Conference on Formal Methods in Computer-Aided Design (FMCAD), 1996.

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S.P. Khatri, A. Narayan, S. C. Krishnan, K. L. McMillan, R. K. Brayton, and A. Sangiovanni-vincentelli. Engineering Change in a Non-Deterministic FSM Setting. In Proceedings of the Design Automation Conference, pages 451-456, June 1996.

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Y. Kukimoto and R. K. Brayton. Hierarchical Timing Analysis under the XBD0 Model. In International Workshop on Logic Synthesis (submitted), May 1997.

18

Y. Kukimoto and R. K. Brayton. Temporal Flexibility in Combinational Circuits. In Design Automation Conference (submitted), June 1997.

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Y. Kukimoto, W. Gosti, A. Saldanha, and R. K. Brayton. Approximate Timing Analysis under the XBD0 Model. In International Workshop on Logic Synthesis (submitted), May 1997.

20

Yuji Kukimoto and Robert K. Brayton. Hierarchical Timing Analysis Under the XBD0 Model. In International Workshop on Logic synthesis (submitted), May 1997.

21

Z-C Liu and R. K. Brayton. Efficient Identification of Non-Robustly Untestable Path Delay Faults. In International Test Conference (submitted), 1997.

22

Z-C Liu and R. K. Brayton. Timed Binary Decision Diagrams. In International Workshop on Logic synthesis (submitted), 1997.

23

Narayan, Khatri, Jain, Fujita, Brayton, and Sangiovanni-Vincentelli. A Study of Composition Schemes for Mixed Apply/Compose Based Construction of ROBDDs. In Ninth International Conference on VLSI Design, pages 249-253, Bangalore, India, Jan. 1996.

24

Mukul Prasad, Desmond Kirkpatrick, R.K. Brayton, and Alberto L. Sangiovanni-Vincentelli. Domino Logic Synthesis and Technology Mapping. In International Workshop on Logic Synthesis (submitted), May 1997.

25

Rajeev K. Ranjan, Wilsin Gosti, and Robert K. Brayton. Dynamic Variable Reordering in a Breadth-First Based BDD Package: Challenges and Solutions. In International Workshop on Logic Synthesis (submitted), Lake Tahoe, California, USA, May 1997.

26

Rajeev K. Ranjan, Jagesh V. Sanghavi, Robert K. Brayton, and Alberto Sangiovanni-Vincentelli. Using Network of Workstations for Efficient Binary Decision Diagram Manipulation. In International Conference on Circuits and Computers (ICCD), Austin, Texas, USA, October 1996.

27

Jagesh V. Sanghavi, Rajeev K. Ranjan, Robert K. Brayton, and Alberto Sangiovanni-Vincentelli. High Performance BDD Package Based on Exploiting Memory Hierarchy. In Design Automation Conference, June 1996.

28

Serdar Tasiran, Rajeev Alur, Robert P. Kurshan, and Robert K. Brayton. Verifying Abstractions of Timed Systems. In CONCUR '96: 7th International Conference on Concurrency Theory, volume 1119, pages 546-562, Pisa, Italy, August 1996. Springer-Verlag.

29

Serdar Tasiran and Robert K. Brayton. STARI: A Case Study in Compositional and Hierarchical Timing Verification. In CAV '97: International Conference on Computer-Aided Verification (submitted), 1997.

30

S. Yamashita, H. Sawada, and A. Nagoya. A New Method to Express Functional Permissibilities for LUT based FPGAs and Its Applications. In International Conference on Computer Aided Design, pages 254-261, November 1996.